Semiconductor device that minimizes the leakage current associat

Details Semiconductor device that minimizes the leakage current associat Semiconductor device that minimizes the leakage current associat

1987-05-12

1988-12-13

Larkins, William D.

357 2311, H01L 2712, H01L 2978

Patent

active

047914645

ABSTRACT:
A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor island such that the gate electrode extends over the sidewalls of the island. Diodes are formed between the source and drain regions and the portions of the channel region along the sidewalls to electrically isolate the top transistor from the parasitic edge transistors.

REFERENCES:
patent: 3890632 (1975-06-01), Ham et al.
patent: 4015279 (1977-03-01), Ham
patent: 4054894 (1977-10-01), Heagerty et al.
patent: 4054895 (1977-10-01), Ham
patent: 4070211 (1978-01-01), Harari
patent: 4178191 (1979-12-01), Flatley
patent: 4185319 (1980-01-01), Stewart
patent: 4252574 (1981-02-01), Fabula
patent: 4393572 (1983-07-01), Policastro et al.
Stewart, "CMOS/SOS EAROM Memory Arrays", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 5, pp. 860-864, Oct. 1979.

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