Cryptography – Key management – Having particular key generator
Patent
1994-05-18
1996-06-25
Barron, Jr., Gilberto
Cryptography
Key management
Having particular key generator
380 21, 380 49, 380 50, H04L 912
Patent
active
055309593
ABSTRACT:
A self-synchronizing scrambler/descrambler arrangement operates in two modes. In the first, or start-up mode, predetermined data is coupled to the scrambler and transmitted to the descrambler. This data is used to "seed", i.e., load, storage devices in the scrambler and descrambler with the same information. After a predetermined time interval, the start-up mode is terminated, and the scrambler and descrambler each operate in a steady-state mode. In this mode, the information loaded in the scrambler and descrambler devices are used to form the scrambler and descrambler key signals. Advantageously, in the steady-state mode, the occurrence of transmission errors does not effect the contents of the storage devices in the scrambler and descrambler. Hence, the prior art problem of error multiplication is avoided. In applications where a number of coded and multiplexed data channels are communicated over the communications channel linking the scrambler and descrambler, this approach allows the use of a single scrambler/descrambler without degrading the coding benefits.
REFERENCES:
patent: 3920894 (1975-11-01), Shirley et al.
patent: 4304962 (1981-12-01), Fracassi et al.
patent: 4663500 (1987-05-01), Okamoto et al.
patent: 4817148 (1989-03-01), Lafferty et al.
patent: 4856063 (1989-08-01), McCalmont
patent: 5235645 (1993-08-01), Stocker
patent: 5241602 (1993-08-01), Lee et al.
patent: 5321754 (1994-06-01), Fisher et al.
Hewlett-Packard Journal, Mar. 1976, USA. vol. 27, No. 7, ISSN 0018-1153, pp. 18-24, "A 50-Mbit/s pattern generator and error detector for evaluating digital communications system performance" by I. R. Young et al. Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.
Nachrichtentechnische Zeitschrift, Dec. 1974, West Germany, vol. 27, No. 12, ISSN 0027-707X, Muller, H.; "Bit sequence independence through scramblers in digital communication systems", p. 476, left column, line 37-line 56, figures 2,6. Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.
Patent Abstracts of Japan, vol. 005 No. 198 (E-087), 16 Dec. 1981 & JP-A-56 122542 (Fujitsu Ltd; Others: 01, 26 Sep. 1981 *Abstract* Comment: Astract listed as technological background on European Search Report for European Application No. 95303159.8.
AT&T Technical Journal, Sep.-Oct. 1986, USA, vol. 65, No. 5, ISSN 8756-2324, pp. 123-136, Doowhan Choi: "Parallel scrambling techniques for digital multiplexers" Comment: Listed as particularly relevant if combined with another document of the same category, on European Search Report for European Application No. 95303159.8.
European Search Report dated Aug. 31, 1995, regarding EPO Application No. EP 95303159.8.
W. Wesley Peterson and E. J. Weldon, Jr., "Error-Correcting Codes", Second Edition, Jul. 1981, The MIT Press, pp. 206-211, 472-492.
AT&T Corp.
Barron Jr. Gilberto
Opalach Joseph J.
LandOfFree
Self-synchronizing scrambler/descrambler without error multiplic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-synchronizing scrambler/descrambler without error multiplic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-synchronizing scrambler/descrambler without error multiplic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2198748