Process for controlling gate/drain overlapped length in lightly-

Details Process for controlling gate/drain overlapped length in lightly- Process for controlling gate/drain overlapped length in lightly-

1996-06-10

1998-06-09

Niebling, John

Fishing, trapping, and vermin destroying

437 40, 437 41, H01L 21265

Patent

active

057632855

ABSTRACT:
A process for forming a lightly-doped drain (LDD) structure in a MOSFET or other semiconductor device. A first polysilicon layer is deposited over a thin gate oxide layer formed on a substrate. The first polysilicon layer is etched to form a first gate region. The substrate is then doped adjacent the gate region to form a drain region having a relatively low impurity concentration. The first polysilicon gate region is removed and a second polysilicon layer is applied to the substrate. The second layer is etched to form a second gate region which will serve as the actual gate region for the MOSFET device. The drain region is then doped a second time to form an LDD structure in which a portion of the drain region underlying the second gate region remains lightly doped while another portion of the drain region exposed to the second doping becomes more heavily doped. The difference in length between the first and second gate regions is used to set the gate/drain overlapped length. The process may be used to form a fully-overlapped LDD structure or may include steps for forming an oxide spacer adjacent the second gate region to thereby produce a partially-overlapped LDD structure.

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