System and method for computer interface board identification by

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395284, 364DIG1, 3642801, 364DIG2, 36492793, 3649294, G06F 900, G06F 1100, G06F 1128

Patent

active

055308953

ABSTRACT:
A system and method for automatically identifying and configuring interface boards connected to a computer bus is disclosed. Each interface board contains a pair of interface ports that can be addressed by the system and a unique identification address. The interface boards are instructed to serially read the identification address and place a logic 10 in the two least significant bits of the data bus if the first data bit is a logic one. The serial read instruction is performed twice for each data bit in the identification address with a logic 01 data pattern placed on the data bus for the second serial read to assure that a floating data bus is not causing false readings. If no interface board responds to any particular read identification instruction, the system assigns a logic zero for that particular bit of the identification address. Any interface board not having a logic one for a particular first data bit in the identification automatically places itself in a disabled state if the first and second serial read instructions indicate that another interface board did have a logic one for that particular data bit of the identification address. By the time that the system has read all of the identification bits, one and only one interface board will have been identified and enabled. The system can read registers on the interface board to determine which resources are required for operation of that board and assigns parameters such as I/O address, interrupt line, and data channel line. The system enables the other previously disabled interface boards and repeats the identification instructions until all interface boards have been identified and configured.

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