Method and apparatus for multiple memory bank selection

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395312, 395476, 395478, 395495, 3642436, 36492692, 364959, 364DIG1, 36518902, 36523002, 36523003, 36528006, G06F 1206, G06F 1300

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055308368

ABSTRACT:
In one aspect a memory bank selection system includes two asynchronous RAS pins and a single CAS pin, a switching circuit for each memory bank and a bank address decoder with an output to each switching circuit. The RAS pins are available to all of the switching circuits. A given switching circuit selects its associated bank if an active RAS signal is present and the bank address decoder output was sent thereto. The number of memory banks that can be simultaneously active directly depends on the number of RAS inputs. In another aspect, the number of CAS pins is equal to the number of asynchronous RAS pins.

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