Hit enhancement circuit for page-table-look-aside-buffer

Details Hit enhancement circuit for page-table-look-aside-buffer Hit enhancement circuit for page-table-look-aside-buffer

1992-05-12

1996-06-25

Moore, David K.

G06F 1210

Patent

active

055308236

ABSTRACT:
A virtual memory computing system is provided with a novel table-look-aside-buffer (TLB). The table-look-aside-buffer is located in cache memory and provides high speed verification that a page address being accessed by the instruction processor is present in the high speed mass storage unit (MSU) of the computer system. In the event of a page miss in the TLB, the control circuits associated with the TLB fetch a page descriptor and generate a translated real page address which is stored in the TLB in an invalidated (decelerated) or non-degraded and least recently used address.

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