Patent
1992-07-29
1996-06-25
Lane, Jack A.
395416, 395417, G06F 1210
Patent
active
055308210
ABSTRACT:
A method of virtual memory addressing control and information apparatus therefor for making a virtual address translation mechanism independently operate in the operating system of a virtual memory controlling architecture. In an information processing apparatus which employs the present invention, the address translating section is separated from the kernel of the operating system (OS) as an address translation server and they communicate with each other by communication messages. The address translation server calculates a physical address with reference to a process page table and system page table upon reception of a process identifier and virtual address from the OS kernel.
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patent: 5063500 (1991-11-01), Shorter
patent: 5129071 (1992-07-01), Yamagata
Mano, Morris; Computer System Architecture; .COPYRGT.1982; pp. 428-429 & 495-501.
Canon Kabushiki Kaisha
Lane Jack A.
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