Failure analysis device for memory devices

Details Failure analysis device for memory devices Failure analysis device for memory devices

1994-07-26

1996-06-25

Beausoliel, Jr., Robert W.

39518313, G06F 1100, G01R 3126

Patent

active

055308058

ABSTRACT:
A physical image converting circuit is used in a memory tester for or an integrated circuit tester analyzing the failure of storage devices to be measured, in which data are read as logical images from each of the corresponding storage regions to each input/output bit and are stored in each of the corresponding storage regions to each input/output bit of a failure analysis memory used for failure analysis. The physical image converting circuit converts the logical image of the readout data from the failure analysis memory into physical images so that the readout data corresponds to a physical position on a wafer chip of the failure analysis memory. The physical image converting circuit includes a counter, an address converting circuit, a failure analysis memory, and a selector. The counter generates increment addresses corresponding to at least a storage capacity of failure analysis memory. The address converting circuit generates data X and Y for specifying X and Y addresses and data P for specifying the input/output bit of the failure analysis memory based on the increment addresses. The selector selects the specified data by the data P among the readout data from the corresponding storage region of the failure analysis memory to the specified X and Y addresses by the data X and Y.

REFERENCES:
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patent: 4958345 (1990-09-01), Fujisaki
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patent: 5146545 (1992-09-01), Maruyama
patent: 5177692 (1993-01-01), Yano
patent: 5214654 (1993-05-01), Oosawa

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