Serial data mode circuit for a memory

Details Serial data mode circuit for a memory Serial data mode circuit for a memory

1982-09-23

1984-11-20

Smith, Jerry

Boots, shoes, and leggings

364200, G06F 104

Patent

active

044843089

ABSTRACT:
A serial data mode circuit, which provides valid data on a falling edge of a data valid signal, uses time between falling edges to prepare for the next falling edge in order to reduce the time between when a falling edge of the data valid signal occurs and when data actually becomes valid. A plurality of interconnected flip-flops selectively enable data latches containing data in response to a rising edge of the data valid signal. The data is then provided to a tri-state driver prior to the falling edge of the data valid signal. The tri-state driver is then enabled in response to the falling edge of the data valid signal.

REFERENCES:
patent: 4079456 (1978-03-01), Lunsford et al.
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4365295 (1982-12-01), Katzman et al.
patent: 4366558 (1982-12-01), Homma et al.

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