Boots – shoes – and leggings
Patent
1982-09-03
1984-11-20
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1516
Patent
active
044842732
ABSTRACT:
A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas.
The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors.
Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.
REFERENCES:
patent: 4204251 (1980-05-01), Brudevold
patent: 4249093 (1981-02-01), Henig
Budwey Michael J.
Karp Richard A.
Nolan, Jr. James M.
Stiffler Jack J.
Wallace David A.
Sequoia Systems, Inc.
Zache Raulfe B.
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