High speed, master/slave latch transceiver having a directly-dri

Details High speed, master/slave latch transceiver having a directly-dri High speed, master/slave latch transceiver having a directly-dri

1990-12-28

1993-09-28

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307480, H03K 3289

Patent

active

052489051

ABSTRACT:
A multi-bit latch transceiver is designed to meet the IEEE 1194.1 standard for backplane transceiver logic as specified in the IEEE 896.2 Futurebus+ specification. The latch transceiver features support for live insertion, low skew, controlled rise/fall time (2ns-5ns) and glitch free power-up/down protection. The transceiver utilizes on-chip latches and a built-in bandgap reference that provides very accurate thresholds. Unique slave stage logic in the transceiver's driver stage provides preset input conditions to the slave latch such that data is instantly clocked to the driver output when the driver is enabled, thus reducing propagation delay.

REFERENCES:
patent: 3603815 (1971-09-01), Rao
patent: 4258273 (1981-03-01), Straznicky et al.
patent: 4900949 (1990-02-01), Saitoh
patent: 5017808 (1991-05-01), Ueno et al.
Holt, "Electronic Circuits: Digital and Analog", John Wiley & Sons, New York, 1978, pp. 176-177.
Motorola Technical Developments; vol. 5, No. 1, Oct. 1985, Schaumburg, IL; pp. 54-55; Mark Bluhm; "A High Speed Output Buffer".
IBM Technical Disclosure Bulletin; vol. 33, No. 7, Dec. 1990, New York, US pp. 185-189, "Circuit Scheme to Improve Chip Data Hold Time".

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