Method of making a contact programmable double level polysilicon

Details Method of making a contact programmable double level polysilicon Method of making a contact programmable double level polysilicon

1980-02-28

1982-04-27

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

148187, H01L 2122, H01L 2128

Patent

active

043263291

ABSTRACT:
A contact programmable, small cell area MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines are metal, gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", by presence or absence of a contact engaging the polysilicon gate over the thin gate oxide.

REFERENCES:
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patent: 3914855 (1975-10-01), Cheney et al.
patent: 3985591 (1976-10-01), Arita
patent: 4055444 (1977-10-01), Rao
patent: 4059826 (1977-11-01), Rodgers
patent: 4151020 (1979-04-01), McElroy
patent: 4198693 (1980-04-01), Kuo
patent: 4208781 (1980-06-01), Rao et al.
patent: 4219836 (1980-08-01), McElroy

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