Reference voltage generating circuit of semiconductor memory dev

Details Reference voltage generating circuit of semiconductor memory dev Reference voltage generating circuit of semiconductor memory dev

1994-07-27

1996-06-25

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327538, 327541, 327543, G05F 302

Patent

active

055303978

ABSTRACT:
A reference voltage generating circuit of a DRAM includes a current mirror circuit constituted of first to fourth transistors. The gate of the third transistor is connected to the source of a fifth transistor. When a zero-power on reset signal, which becomes L on turn-on of the power supply, and becomes H after a predetermined period, is applied to the gate of the fifth transistor, and an external power supply voltage is forced to be applied to the gate of the third transistor on turn-on of the power supply, a reference voltage following the rise of the external power supply voltage is provided from the output of the current mirror circuit.

REFERENCES:
patent: 4495425 (1985-01-01), McKenzie
patent: 5155384 (1992-10-01), Ruetz
patent: 5243231 (1993-09-01), Baik
patent: 5300822 (1994-04-01), Sugahara et al.
patent: 5304861 (1994-04-01), Fruhauf et al.
patent: 5391979 (1995-02-01), Kajimoto et al.
Hideto Hidaka et al, "A 34-ns 16-Mb DRAM with Controllable Voltage Down Converter", IEEE Journal of Solid-State Circuits, vol. 27, No. 7, Jul. 1992, pp. 1020-1026.

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