Threshold adjustment in fabricating vertical DMOS devices

Details Threshold adjustment in fabricating vertical DMOS devices Threshold adjustment in fabricating vertical DMOS devices

1992-03-20

1993-09-28

Thomas, Tom

Fishing, trapping, and vermin destroying

437 30, 437149, 148DIG126, H01L 21266

Patent

active

052486273

ABSTRACT:
A process for fabricating a p-channel VDMOS transistor includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming body regions. The threshold voltage of the VDMOS devices is adjusted subsequent to both gate formation and the high temperature, long duration body diffusion by implanting a suitable p-type dopant into the VDMOS channel through the insulated gate, after formation thereof. Since the gate is formed prior to threshold adjust, high temperature processing and long duration diffusions requiring the presence of the gate may be completed prior to threshold adjust, without risk to the adjusted device threshold.

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