Boots – shoes – and leggings
Patent
1994-03-08
1995-08-15
Malzahn, David H.
Boots, shoes, and leggings
326 37, G06F 738
Patent
active
054425778
ABSTRACT:
An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or reduced-width operands. The Boolean logic unit is constructed from 4:1 multiplexers (muxes), one mux for every bit in a full-width operand. The operands or constants are input to the select inputs for the muxes while signals representing the truth table for a predetermined Boolean operation are inputted to the four data inputs of each of the muxes. This allows for many different kinds of Boolean operations to be executed by the Boolean logic unit; each type of Boolean operation called for by an instruction opcode will have a corresponding set of truth table signals for input to the muxes. Sign-extension can be combined with the Boolean operation by using the sign bit of the reduced-width operand to select one of two modified sets of truth-table signals. The selected set of truth-table signals is applied to the data inputs of the muxes. An upper section of the truth-table sets has the sign bit of the reduced width operand encoded into the truth-table sets themselves. The integer arithmetic unit uses exclusive-OR gates, controlled by the sign bit, to selectively invert the reduced width operand. The output, which is always a positive number, is extended with zeros, then selectively inverted again before being added to a second operand in an adder. Addition or subtraction incorporating the sign-extension of one operand is thus possible with the modified integer arithmetic unit.
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Auvinen Stuart T.
Exponential Technology Inc.
Malzahn David H.
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