Pulse or digital communications – Repeaters – Testing
Patent
1980-09-16
1982-08-31
Safourek, Benedict V.
Pulse or digital communications
Repeaters
Testing
333 18, H04L 2503, H03K 5159, H04B 304
Patent
active
043476155
ABSTRACT:
The presence of a d.c. offset in the input signal to an adaptive equalizer for a high speed modem must be removed before a valid signal enters the equalizer if the "coefficient up-date" algorithm for the equalizer is not to be confused. Normally the d.c compensation is achieved using adjust-on-test resistors or potentiometers which provide for in life adjustments to compensate for ageing drift. The submission envisages the use of an additional adaptive equalizer tap-stage connected to a fixed voltage source. This voltage is multiplied by the additional tap-stage multiplier and summed with the outputs of the other tap-stages in the equalizers accumulator. The error produced from the equalizer decision circuit is correlated with the fixed voltage in the additional tap-stage correlator the output of which controls the gain of the additional tap-stage multiplier thereby compensating for the original d.c. offset of the output of the equalizer accumulator.
REFERENCES:
patent: 3597541 (1971-08-01), Proakis
patent: 3697875 (1972-10-01), Guanella
patent: 3949206 (1976-04-01), Edwards et al.
patent: 3992616 (1976-11-01), Acker
patent: 4011405 (1977-03-01), Ridout et al.
Proceedings of the IEEE; vol. 65, No. 3, Mar. 1977, pp. 444-453, "Echo Cancellation on Time-Variant Circuits", Nicholas Demytko and Kevin S. English.
Plessey Overseas Limited
Safourek Benedict V.
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