Frame alignment circuit

Multiplex communications – Wide area network – Packet switching

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Details

3701052, 3701053, 370106, 375354, 375368, H04J 306

Patent

active

054901472

ABSTRACT:
A frame alignment circuit including at least a first series-to-parallel data converter having a shift register for accumulating series data, a latch circuit for converting the accumulated data into parallel data and a variable counter for dividing a clock signal into a divided clock signal. The frame alignment circuit further includes a pattern detector which detects a frame alignment pattern of the parallel data, a determining circuit which determines a deviation of alignment based on a reference frame alignment signal and the detected frame alignment pattern and a shift controlling circuit for controlling at least a dividing ratio of the variable counter based on a deviation of alignment signal output by the frame alignment circuit.

REFERENCES:
patent: 3909541 (1975-09-01), Bobilin
patent: 4920546 (1990-04-01), Iguchi et al.
patent: 5327434 (1994-07-01), Kubo
Design Considerations of Broadband Access System Components K. Murano, T. Soejima, K. Iguchi, T. Tsuda, M. Ohhata, Globecom '87 pp. 13.6.1-6 1987.

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