Error-correcting and error-detecting system

Details Error-correcting and error-detecting system Error-correcting and error-detecting system

1978-09-05

1980-07-22

Atkinson, Charles E.

Excavating

G06F 1112

Patent

active

042142288

ABSTRACT:
Described is an error-correcting and error-detecting system including a check-bits generating circuit which is formed in accordance with a (k,l) type check matrix, such (k,l) type check matrix being formed from an (m,l) type reference sub-matrix (where m<k) and one or more (m,l) type sub-matrices, and each of the (m,l) type sub-matrices being derived from the (m,l) type reference sub-matrix by replacing unit-matrices of the (m,l) type reference sub-matrix with each other in accordance with a circular shift; wherein a desired check-bits code of an input data is obtained by multiplying the input data with respective reference sub-matrix and sub-matrices and by rearranging respective multiplied results produced from the respective rows of these reference sub-matrix and sub-matrices.

REFERENCES:
patent: 3825893 (1974-07-01), Bossen et al.
patent: 3893070 (1975-07-01), Bossen et al.
patent: 3893071 (1975-07-01), Bossen et al.
patent: 3949208 (1976-04-01), Carter
patent: 4077028 (1978-02-01), Lui et al.
patent: 4099160 (1978-07-01), Flagg
Hong and Patel, A General Class of Maximal Codes for Computer Applications, IEEE Trans. on Computers, vol. C-21, No. 12, Dec. 1972, pp. 1322-1331.

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