Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1980-05-21
1982-08-31
Rutledge, L. Dewayne
Metal working
Method of mechanical manufacture
Assembling or joining
29578, 148175, 148187, 156612, 156613, 156647, 156657, 156662, 357 20, 357 22, 357 50, 357 55, 357 56, 357 60, H01L 21205, H01L 21302
Patent
active
043465137
ABSTRACT:
A method of fabricating a semiconductor integrated circuit device wherein a substrate having a particular crystallographic orientation is selectively etched so as to form surface depressions of different depths. An epitaxial layer is grown from a Si--H--Cl system on the surface of the substrate having the surface depressions formed therein. The epitaxial layer is grown under conditions effective to achieve faster lateral growth than vertical growth so as to form the epitaxial layer with regions of three different thicknesses. Subsequently, additional regions of the semiconductor integrated circuit are formed in the epitaxial layer regions of different thicknesses so as to complete the device.
REFERENCES:
patent: 3370995 (1968-02-01), Lowery et al.
patent: 3412296 (1968-11-01), Grebene
patent: 3456169 (1969-07-01), Klein
patent: 3511702 (1970-05-01), Jackson, Jr. et al.
patent: 3740276 (1973-06-01), Bean
patent: 3755012 (1973-08-01), George et al.
patent: 3764409 (1973-10-01), Nomura et al.
patent: 3793712 (1974-02-01), Bean et al.
patent: 3938176 (1976-02-01), Sloan
patent: 4056413 (1977-11-01), Yoshimura
patent: 4089021 (1978-05-01), Sato et al.
patent: 4141765 (1979-02-01), Druminski et al.
patent: 4219719 (1980-08-01), Frosien et al.
Doo; V. Y., "Junction Isolation . . . By Etch and Regrowth . . . ", I.B.M. Tech. Discl. Bull., vol. 8, No. 4, Sep. 1965, pp. 668-669.
Agusta et al., "Monolithic Integrated Semiconductor . . . ", I.B.M. Tech. Discl. Bull., vol. 9, No. 5, Oct. 1966, pp. 546-547.
Shimbo et al., "Defect-Free Nucleation of Silicon . . . ", J. of Crystal Growth, vol. 23, pp. 267-274, 1974.
Nishizawa et al., "Anisotropy in Growth Rates of Silicon . . . ", J. Crystal Growth, vol. 31, 1975, pp. 290-298.
Nishizawa Jun-ichi
Shimbo Masafumi
Adams Bruce L.
Burns Robert E.
Kabushiki Kaisha Daini Seikosha
Lobato Emmanuel J.
Rutledge L. Dewayne
LandOfFree
Method of fabricating semiconductor integrated circuit device ut does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating semiconductor integrated circuit device ut, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor integrated circuit device ut will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2179198