Fault tolerant monolithic multiplier

Details Fault tolerant monolithic multiplier Fault tolerant monolithic multiplier

1979-10-22

1981-11-24

Malzahn, David H.

Boots, shoes, and leggings

364758, G06F 1120, G06F 752

Patent

active

043028195

ABSTRACT:
A fault tolerant multiplier which utilizes a plurality of full adder rows has the ability to permanently deselect a row when a fault is detected in its initial testing. An extra row is provided to allow this deselection and transfer gates are provided between each row to shift the sum and carry logic on to the next row at the point of the deselected row and all rows therebeyond.

REFERENCES:
patent: 3665174 (1972-05-01), Bouricius et al.
patent: 3900724 (1975-08-01), McIver et al.
Pradhan, "Fault-Tolerant Carry-Save Adders", IEEE Trans. on Computers, Dec. 1974, pp. 1320-1322.
Waser, "High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing", Computer, Oct. 1978, pp. 19-29.

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