Self-limiting erasable memory cell with triple level polysilicon

Details Self-limiting erasable memory cell with triple level polysilicon Self-limiting erasable memory cell with triple level polysilicon

1979-01-05

1981-11-24

Wojciechowicz, Edward J.

357 23, 357 45, 357 51, 357 59, 29576R, 29577C, 29578, H01L 2702, B01J 1700

Patent

active

043027660

ABSTRACT:
A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.

REFERENCES:
patent: 3744036 (1973-07-01), Frohman-Bentchrowsky
patent: 4099196 (1978-07-01), Simko

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