Patent
1996-02-05
1997-12-16
Moore, David K.
3954211, 39542104, 39542109, G06F 926, G06F 1206
Patent
active
056995458
ABSTRACT:
A system and method for generating row addresses for a memory structure on a column by column basis. In accordance with the novel method, a column read start address (SC) is subtracted from a column address (COL) to provide a column offset. Next, the column offset is multiplied by the multiplicative inverse of the skip period in modulo (SPM.sup.-1) to provide a first product. The first product is multiplied by a skip period between data strings to provide a second product. The second product is divided by a number (NC) which represents the number of columns in the memory structure to provide a first quotient. Finally, a base row address of a first row to be read (BRA) is added to the first quotient to provide a row address (RA). In a specific embodiment, the step of multiplying the column offset by the multiplicative inverse of the skip period in modulo includes the step of converting the first product to a modulo product. And the step of adding the base row address of a row to be read to the first quotient includes the step of adding a wrapping bit (N) to the base row address and the first quotient to provide the row address.
REFERENCES:
patent: 4884069 (1989-11-01), Farand
patent: 5150467 (1992-09-01), Hayes et al.
Kuwanoe Gordon W.
Wong Gary A.
Alkov Leonard A.
Denson-Low Wanda K.
Hughes Electronics
Moore David K.
Nguyen Than V.
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