Method of forming CMOS devices using independent thickness space

Fishing – trapping – and vermin destroying

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437 34, 437 48, 437 52, 437 56, H01L 218242

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054895464

ABSTRACT:
NMOS and PMOS devices are formed in a split-polysilicon CMOS process using independent thickness transistor gate spacers, and using a silicon nitride layer as a mask for the p-channel region during an n+ source/drain implant step of the n-channel region. The p-channel spacer is formed significantly thicker than the n-channel spacer, thereby reducing lateral diffusion of p-type dopant species under the p-channel gate and avoiding short channel effects to improve device reliability and performance. P-channel transistor junction depth and lateral diffusion is further reduced by performing an n-channel arsenic source/drain implant before the p-channel source/drain boron difluoride implant, although the p-channel transistor gate is etched before the n-channel gate. Moreover, since the p-channel transistor gate is etched before the n-channel gate, the p-channel gate sidewalls are reoxidized as well as the n-channel gate sidewalls for improved gate oxide integrity.

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