Rounding unit for use in arithmetic processing of floating point

Details Rounding unit for use in arithmetic processing of floating point Rounding unit for use in arithmetic processing of floating point

1985-07-12

1989-01-03

Harkcom, Gary V.

Boots, shoes, and leggings

364748, G06F 738

Patent

active

047962178

ABSTRACT:
A rounding unit for use in arithmetic processing of register floating point data. The rounding unit comprises a mantissa part register for storing the mantissa part of the floating point data, an exponent part register for storing the exponent part of the floating point data, a judging circuit for judging whether the rounding operation is raising or truncating, a mantissa part incrementer for incrementing the mantissa part of the floating point data and outputting a carry signal when it is overflowed, an exponent part incrementer for incrementing the exponent part of the floating point data and a selection circuit which, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, orders the mantissa part register to store a constant data of which the most significant bit is "1" and the other bits are "0", when the rounding operation is raising and the carry signal is present. For generating the constant data, a constant register or an adjusting means is employed. The rounding unit executes the rounding operation of floating point data by hardware and thus it operates at a very high speed.

REFERENCES:
patent: 4295203 (1981-10-01), Joyce
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4386413 (1983-05-01), Vignes et al.
patent: 4468748 (1984-08-01), Blaw et al.
patent: 4484259 (1984-11-01), Palmer et al.
patent: 4528640 (1985-07-01), Criswell
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4589067 (1986-05-01), Porter et al.

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