Processor microarchitecture for efficient dynamic scheduling and

Details Processor microarchitecture for efficient dynamic scheduling and Processor microarchitecture for efficient dynamic scheduling and

1995-12-22

1997-12-16

Treat, William M.

395394, 395800, G06F 938

Patent

active

056995377

ABSTRACT:
A processor microarchitecture for efficient dynamic instruction scheduling and execution. The invention includes a predetermined number of independent dispatch queues. The invention also includes a cluster of execution units coupled to each dispatch queue such that the dispatch queue and the corresponding cluster of execution units forms an independent micropipeline. Chain-building and steering logic coupled to the dispatch queues identifies a consumer instruction relying on a producer instruction for an operand, and issues the consumer instruction to the same dispatch queue as the producer instruction that it is dependent upon. The instructions are issued from the dispatch queue to the corresponding cluster of execution units. In one embodiment, the output of each execution unit in the cluster is routed to the inputs of all execution units in the cluster such that the result of executing the producer instruction is readily available as an operand for execution of the consumer instruction.

REFERENCES:
patent: 5471593 (1995-11-01), Branigin
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5553256 (1996-09-01), Fetterman et al.
patent: 5559976 (1996-09-01), Song
patent: 5592679 (1997-01-01), Yung
patent: 5604753 (1997-02-01), Bauer et al.
patent: 5615350 (1997-03-01), Hesson et al.
Harry Dwyer III, A Multiple, Out-of-Order, Instruction Issuing System for Superscalar Processors, Phd. Dissertation, Cornell University, Aug. 1991, pp. 16-19.
"The Metaflow Architecture," pp. 10-13 and 63-73, by Val Popescu, Merle Schultz, John Spracklen, Gray Gibson, Bruce Lightner, and David Isaman, IEEE Micro, 1991.
Johnson, Mike, "Superscalar Microprocessor Design", Prentice Hall, 1991.

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