Microprocessor cache memory way prediction based on the way of p

Details Microprocessor cache memory way prediction based on the way of p Microprocessor cache memory way prediction based on the way of p

1994-10-14

1997-06-17

Chan, Eddie P.

G06F 1208

Patent

active

056405324

ABSTRACT:
In a microcomputer system using a multiple-way cache memory subsystem, the way of the next microprocessor operation is predicted, and either the output enables of the cache are predriven, or, in a single-bank multiple-way cache, the address bit which acts as a way selection is appropriately set. The way prediction used is based not on the address being accessed in the cache, but instead on the last processor code read, or the last processor code or data read. This permits the cache memory subsystem to respond more quickly on hits to the appropriate way, and also allows for slower cache memories to be used without reducing performance.

REFERENCES:
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patent: 5293603 (1994-03-01), MacWilliams et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5392414 (1995-02-01), Yung
patent: 5418922 (1995-05-01), Liu

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