Microprocessor peripheral access control circuit

Details Microprocessor peripheral access control circuit Microprocessor peripheral access control circuit

1983-12-23

1987-09-08

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1300

Patent

active

046928952

ABSTRACT:
A microprocessor system is adapted to permit the accessing of peripheral devices that have slow data bus release times without acquisition conflicts by placing the microprocessor in the hold state after the data acquisition. Logic circuitry responsive to the hold state supplies control signals to the peripheral devices over the bus during the hold state. At the end of one hold state, normal operation is resumed.

REFERENCES:
patent: 3753232 (1973-08-01), Sporer
patent: 4050096 (1977-09-01), Bennett et al.
patent: 4050097 (1977-09-01), Miu et al.
patent: 4153941 (1979-05-01), Caddell
patent: 4386401 (1983-05-01), O'Brien
patent: 4414664 (1983-11-01), Greenwood
patent: 4438490 (1984-03-01), Wilder, Jr.
"Memory and I/O Synchronization--The WAIT State," Microprocessors and Programmed Logic, K. L. Short, 1981, pp. 95-97.

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