Method for electric leaf cell circuit placement and timing deter

Details Method for electric leaf cell circuit placement and timing deter Method for electric leaf cell circuit placement and timing deter

1994-04-25

1997-06-17

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, G06F 1750, G06F 1126

Patent

active

056403283

ABSTRACT:
A method for determining the location of electric leaf cell circuits within the architecture of a semiconductor chip includes determination of the longest signal delays through an electric leaf cell circuit by evaluating independent channel connected components, reorganizing the circuit elements of each channel under evaluation into acyclic form, restructuring the acyclic form of channel connected components within the electric leaf cell circuits being structurally positioned in the chip architecture by selected reduction processes, determining input state vectors for each input and output pin connection pair of the electric leaf cell circuit in which an input pin connection state change is reflected in an output connection pin state change, and determining placement of the leaf cell within a semiconductor circuit module with reference to the greatest delay within each leaf cell.

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