Apparatus for load regulation in computer systems

Details Apparatus for load regulation in computer systems Apparatus for load regulation in computer systems

1984-03-12

1987-09-08

Williams, Jr., Archie E.

Boots, shoes, and leggings

370 60, 370 94, 3408255, 379269, G06F 1500, G06F 900, H04J 324

Patent

active

046928600

ABSTRACT:
An apparatus in a computer-controlled telecommunication system for carrying out load regulation with the aid of a queueing system for insuring that, in transmission of data information between a regional processor (RP) and a central processor (CP), all program levels in said central processor are guaranteed a positive share of the processor capacity. In the regional processor transmitter (RP) are included a transmitter memory (SM) and a ticket memory (BM). A regulator unit (R) is included in the central processor or receiver (CP) and comprises a plurality of regulator members (S-N), where each is utilized on a given program level and cooperates with a job buffer (JBB-JBN) associated with the program level. The regulator member (S) corresponds to the highest program level and the member (N) to the lowest. Each member, apart from the last one, contains three memory units (KB,KM,KK) in the form of counters. The last member (N) in the chain of regulator members contains only one counter (KB). Emptying of the paper baskets, through associated buffers, guarantees an interruption in the processing of signals on higher program levels and enables processing of signals on lower levels instead.

REFERENCES:
patent: 4080649 (1978-03-01), Calle et al.
patent: 4145735 (1979-03-01), Soga
patent: 4172284 (1979-10-01), Heinrich et al.
patent: 4220990 (1980-09-01), Alles
patent: 4262331 (1981-04-01), Freeland et al.
patent: 4481583 (1984-11-01), Mueller

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