Method and apparatus for fault testing a pipelined processor

Details Method and apparatus for fault testing a pipelined processor Method and apparatus for fault testing a pipelined processor

1995-05-26

1997-12-16

Hua, Ly V.

Excavating

371 225, G06F 1100

Patent

active

056995067

ABSTRACT:
A method and apparatus for fault testing a pipelined processor. In test mode, the stage registers are reconfigured as multiple input shift registers by switching in a few exclusive-OR gates. Also, the execute stage is prevented from executing any instructions. A unique sequential test sequence of instructions are run through the processor at normal speed. It is known that a particular test sequence (and thus a unique sequential input pattern to the MISR, assuming no faults) will result in a unique signature pattern existing in the MISR at the end of the sequence. If the signature pattern is not found in the MISR at the end of the test sequence, then it is known that a fault exists on the chip.

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