Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1979-12-21
1982-06-29
Roy, Upendra
Metal working
Method of mechanical manufacture
Assembling or joining
29576B, 148 15, 148187, 357 41, 357 59, 357 91, H01L 21425, G11C 1140
Patent
active
043366473
ABSTRACT:
An MOS read only memory or ROM formed by the standard N-channel silicon gate manufacturing process uses a cell structure which allows implant programming after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon strips and output and ground lines are metal strips perpendicular to the address lines; these metal strips make contact to the sources and drains defined by N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by selective ion implant through the polysilicon gates and thin gate oxide, using photoresist as a mask, after application of the metal level. The ion implant is not required to penetrate through the metal lines.
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patent: 4208780 (1980-06-01), Richman
patent: 4230504 (1980-10-01), Kuo
patent: 4235010 (1980-11-01), Kawagoe
patent: 4257826 (1981-03-01), Matalone, Jr.
patent: 4257832 (1981-03-01), Schwabe et al.
Graham John G.
Roy Upendra
Texas Instruments Incorporated
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