Selectable multi-input CMOS data register

Details Selectable multi-input CMOS data register Selectable multi-input CMOS data register

1986-04-28

1987-09-08

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

377 79, H03K 3356, G11C 1140

Patent

active

046926348

ABSTRACT:
A CMOS data register includes a master stage and a slave stage. The master stage is formed of first transfer gates and first storage devices. The slave stage is formed of second transfer gates, second storage devices and third transfer gates. The transfer gates and storage devices are formed of MOS transistors of one conductivity which decreases layout complexity and reduces the amount of chip area required. The data register is formed of a fewer number of transistor components, thereby reducing the loading on the clock signals.

REFERENCES:
patent: 3395292 (1968-07-01), Bogert
patent: 3821711 (1974-08-01), Crowle
patent: 4031415 (1977-06-01), Redwine et al.
patent: 4132904 (1979-01-01), Harari

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