Clock regenerator comprising a reversible shift register and a c

Details Clock regenerator comprising a reversible shift register and a c Clock regenerator comprising a reversible shift register and a c

1976-10-12

1978-05-02

Richardson, Robert L.

Telegraphy

Systems

Line-clearing and circuit maintenance

H04L 700

Patent

active

040876276

ABSTRACT:
A clock regenerator for a binary input which comprises a shift register having successively coupled first stages, a single predetermined stage, and second stages. A frequency divider device responsive to a local oscillation and with a controllable ratio produces timing pulses of a timing period equal to that prescribed number of clock periods which may be unity. Each timing pulse presets a binary signal in the single predetermined stage. The signal is shifted, when a transition occurs in binary values of the input signal within a predetermined interval defined by each timing period. The signal is shifted into the first and second stages if the transition occurs during a leading and a trailing half of each timing period, respectively, the timing pulse thus leading and lagging behind the input signal. The shifted binary signal controls the frequency division ratio to phase-synchronize the timing pulses with the input signal.

REFERENCES:
patent: 3828130 (1974-08-01), Yamaguchi

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