Semiconductor memory system

Details Semiconductor memory system Semiconductor memory system

1986-06-26

1988-10-04

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365189, G11C 1140

Patent

active

047759585

ABSTRACT:
A semiconductor memory system of, typically, the EEPROM type comprising a memory cell including a memory transistor which is typically a SAMOS type non-volatile device having a first threshold voltage higher than a predetermined reference level when the memory transistor is in a state storing a logic "0" bit of data and a second threshold voltage lower than the reference level when the memory transistor is in a state storing the other of the logic "1" bit of data. A control circuit for controlling the control gate of the SAMOS type memory transistor, comprising a combination of transistors arranged to be operative to produce a readout voltage intervening between the reference level and the first threshold voltage, the memory transistor being responsive to the readout voltage for having a first state if the memory transistor has the first threshold voltage and a second state if the memory transistor has the second threshold voltage. A sense amplifier is responsive to each of the first state and the second state of the memory transistor for reading the logic "1" bit of data or the logic "0" bit of data stored therein.

REFERENCES:
patent: 4342099 (1982-07-01), Kuo
patent: 4527257 (1985-07-01), Cricchi
patent: 4586163 (1986-04-01), Koike

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