Parallel processing system apparatus

Details Parallel processing system apparatus Parallel processing system apparatus

1986-05-29

1988-10-04

Harkcom, Gary V.

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364200, G06F 1531

Patent

active

047759526

ABSTRACT:
Configured for accelerated operation of processing elements in a SIMD parallel processing system is disclosed. The output of an exclusive-OR gate is coupled to one input of the element ALU while a first input of the gate is adapted to receive signals intended for the ALU input. Upon loading a `1` bit into a register coupled to a gate second input, signals applied to the gate first input are complemented and applied to the ALU input. As a result, different arithmetic and logic operations can be performed simultaneously by different elements in the processing system in response to a single series of instructions.

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"Digital Computer Arithmetic Design and Implementation" by Joseph J. F. Cavanagh, McGraw-Hill, 1984, pp. 252-258.

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