Cache memory circuit for processing a read request during transf

Details Cache memory circuit for processing a read request during transf Cache memory circuit for processing a read request during transf

1986-02-03

1989-05-30

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1208, G06F 1314

Patent

active

048356786

ABSTRACT:
A cache memory circuit is responsive to a read request to fetch a data block in a block transfer from a main memory to a cache memory. A sequence of data units into which the data block is divided is successively assigned to a plurality of cache write registers. The assigned data units are simultaneously moved to one of sub-blocks of the cache memory during each of write-in durations with an idle interval left between two adjacent ones of the write-in durations. Each state of the sub-blocks is monitored in a controller. During the idle interval, a following read request can be processed with reference to the states of the sub-blocks even when it requests the data block being transferred. In addition, a read address for the following read request may be preserved in a saving address register to process another read request.

REFERENCES:
patent: 3896419 (1975-07-01), Lange et al.
patent: 4169284 (1979-09-01), Hogan et al.
patent: 4381541 (1983-04-01), Baumann, Jr.
patent: 4439829 (1984-03-01), Tsiang
patent: 4467419 (1984-08-01), Wakai
patent: 4511960 (1985-04-01), Boudreau

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