Ensuring data integrity by locked-load and conditional-store ope

Details Ensuring data integrity by locked-load and conditional-store ope Ensuring data integrity by locked-load and conditional-store ope

1990-06-29

1993-03-09

Dixon, Joseph L.

Boots, shoes, and leggings

395375, 395650, 364DIG1, G06F 1300

Patent

active

051931672

ABSTRACT:
A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

REFERENCES:
patent: 4561051 (1985-12-01), Rodman et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5025366 (1991-06-01), Baror
Intel product specification, "i860.TM. 64-Bit Microprocessor", Oct. 1989, pp. 5-1 to 5-72.
Kane, "MIPS R2000 RISC Architecture", Prentice Hall, 1987, pp. 1-1 to 4-11 and pp. A-1 to A-9.
Radin, "The 801 Minicomputer", IBM Research Report, Nov. 11, 1981, pp. 1-23.

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