Patent
1984-03-19
1989-05-30
Larkins, William D.
357 13, 357 22, 357 46, 357 48, H01L 2710, H01L 2970, H01L 2976
Patent
active
048355968
ABSTRACT:
Transistor arrangement with a high collector-emitter breakthrough voltage having a heavily doped emitter zone in a more weakly doped base zone includes an even more weakly doped collector zone having a collector contact diffusion region and a buried layer region, the base zone being embedded in the collector zone, the collector zone being formed of a weakly doped epitaxial layer on a substrate having a type of conduction opposite that of the epitaxial layer, the buried layer region at least partially underlying the base zone.
REFERENCES:
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patent: 4337474 (1982-06-01), Yukimoto
Werner et al., 1981, IEEE ISSCC, DIG. Tech. Papers, pp. 40-41 (Feb. 1981).
Wyland, IBM Tech. Discl. Bulletin, vol. 13, No. 1, Jun. 1970, pp. 204-205.
Hamilton & Howard, Basic Integrated Circuit Engineering (McGraw-Hill, NY, 1975), pp, 4-10.
Bernard Lewis Grung, "Investigation . . . Lock-Layer Transistor", PhD Thesis, U. of Minn., pp. 14, 15, 86-88 (Dissert. Absts. Internat., Sep. 77, pp. 1331B-1332B).
Warner, Jr. et al., Solid State Electronics, Apr. 1975, pp. 323-325, "Bipolar Lock-Layer Transistor".
Greenberg Laurence A.
Larkins William D.
Lerner Herbert L.
Siemens Aktiengesellschaft
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