1987-09-28
1989-05-30
Sikes, William L.
357 55, 357 59, 357 236, H01L 2702, H01L 2906, H01L 2904, H01L 2978
Patent
active
048355895
ABSTRACT:
A random access memory (RAM) cell of a trench within a semiconductor substrate. The RAM cell has a load device in the form of a sidewall around at least part of the perimeter of the trench. The load device should be connected to either one of the source/drain regions or the gate in a field effect transistor (FET). If the load device is a capacitor, using the sidewall structure as one plate and the wall of the trench as the other plate, with a thin dielectric layer between, then a dynamic RAM cell (DRAM) cell with result. On the other hand, if the sidewall load device is a resistor, then a static RAM cell or SRAM will result. The compact nature of the trench sidewall load structure will consume appreciably less lateral space than conventional RAM cells. Additionally, the gate for the FET in the bottom floor of the trench can be formed at the same time and out of the same conductive layer as the conductive sidewall load device, an advantage which saves process steps. The conductive layer may be doped semiconductor material, such as polycrystalline silicon (polysilicon); a metal, such as aluminum; a refractory metal silicide or a combination of these.
REFERENCES:
patent: 4199772 (1980-04-01), Natori et al.
patent: 4727045 (1988-02-01), Cheung et al.
Fisher John A.
Limanek Robert P.
Motorola Inc.
Sikes William L.
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