Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1981-12-04
1984-02-07
Rutledge, L. Dewayne
Metal working
Method of mechanical manufacture
Assembling or joining
29578, 156656, H01L 2128, H01L 21308
Patent
active
044294522
ABSTRACT:
The invention relates to a method of manufacturing field-effect transistors having a self-aligned grid in the submicron range without using a mask of submicron size. The invention is remarkable in that it consists of undercutting the drain electrode at an edge covered with a lacquer over a distance typically smaller than one micron, depositing the source electrode, etching the semiconductor material between the drain electrode and source electrode at the undercut area, and depositing the grid electrode in the cavity thus formed. The invention also relates to field-effect transistors thus obtained.
REFERENCES:
patent: 3675313 (1972-07-01), Driver
patent: 3678573 (1972-07-01), Driver
patent: 3737701 (1973-06-01), Hoeberechts
patent: 3764865 (1973-10-01), Napoli
patent: 3866310 (1975-02-01), Driver
patent: 3898353 (1975-08-01), Napoli
patent: 3920861 (1975-11-01), Dean
patent: 4048712 (1977-09-01), Buiatti
patent: 4063992 (1977-12-01), Hosack
patent: 4075652 (1978-02-01), Umebachi
patent: 4145459 (1979-03-01), Goel
patent: 4261095 (1981-04-01), Dreves
patent: 4266333 (1981-05-01), Reichert
patent: 4318759 (1982-03-01), Trenary
Miller Paul R.
Rutledge L. Dewayne
U.S. Philips Corporation
Zimmerman J. J.
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