Comparator circuit having improved output characteristics

Details Comparator circuit having improved output characteristics Comparator circuit having improved output characteristics

1987-12-10

1989-05-30

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307494, 307548, 307549, H03K 524, H03K 1704

Patent

active

048354171

ABSTRACT:
In a comparator circuit comprising a first power supply terminal means and a second power supply terminal means, a differential stage connected between the first power supply terminal means and the second power supply terminal means, a first input signal having a reference level and a second input signal having a level which is compared with the reference level being input to each of a pair of input terminals of the differential stage, respectively, an output signal having a level which is determined in accordance with the level of the second input signal being output from an output terminal of the differential stage, and an output stage connected to the output terminal of the differential stage, through which output stage the output signal of the differential stage is amplified; a bypass circuit through which a predetermined constant current flows is connected between the output terminal of the differential stage and the second power supply terminal means.
The bypass circuit may be always closed or may be closed only when the output level of the output stage has reached the predetermined value.

REFERENCES:
patent: 3780317 (1973-12-01), Kurata et al.
patent: 3970951 (1976-07-01), Hoffman
patent: 4103249 (1978-07-01), Burdick
patent: 4118640 (1978-10-01), Ochi et al.
patent: 4394587 (1983-07-01), McKenzie et al.
patent: 4438349 (1984-03-01), Shoji
patent: 4527076 (1985-07-01), Matsuo et al.
patent: 4529891 (1985-07-01), Oida
Patents Abstracts of Japan, vol. 9, No. 53 (E-301) [1776], Mar. 7, 1985; & JP-A-59 191 936 (Nippon Denki K.K.) 10-31-84.
Patents Abstracts of Japan, vol. 5, No. 63 (E-54) [735], Apr. 28, 1981; & JP-A-56 14 726 (Matsushita Kenki Sangyo K.K.) 02-13-81.
IEEE Journal of Solid State Circuits, vol. SC-13, No. 6, Dec. 1978, pp. 760-766, Senderowica et al.: "High-performance NMOS operational amplifier".

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