Dual latency status and coherency reporting for a multiprocessin

Details Dual latency status and coherency reporting for a multiprocessin Dual latency status and coherency reporting for a multiprocessin

1994-10-03

1997-03-04

Harvey, Jack B.

395468, 39518504, G06F 1300

Patent

active

056088787

ABSTRACT:
A multiprocessing system utilizes a bus protocol having two response windows. The first response window is at a fixed latency from the transmission of a bus request and/or address, while the second response window, utilized for coherency reporting, is placed a configurable number of clock cycles after the bus request and address to allow for longer access, or snoop, times to perform a cache directory look-up within other bus devices. The first response window reports error or flow control and error status. Furthermore, a method had been described, which implements the reporting of response information in a flexible and high performance manner.

REFERENCES:
patent: 5263153 (1993-11-01), Intrater et al.
patent: 5313627 (1994-04-01), Armini
patent: 5404489 (1995-04-01), Woods et al.
patent: 5463753 (1995-10-01), Fry et al.
patent: 5490253 (1996-02-01), Laha et al.

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