Method of fabricating self-aligned zener diode

Details Method of fabricating self-aligned zener diode Method of fabricating self-aligned zener diode

1987-11-24

1989-05-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437162, 437904, 357 13, H01L 2990

Patent

active

048351113

ABSTRACT:
A method of fabricating a self-aligned zener diode provides for N.sup.+ and P.sup.+ regions having the large dopant concentrations necessary for compatibility with shallow junction silicon gate CMOS devices. A contact region is provided on the substrate, doped with N-type dopant ions, and etched to cover a portion of the region in which a zener diode is to be formed. A P.sup.+ region is implanted using the doped contact region as a mask. Then, N-type dopant ions are diffused from the contact region to the underlying substrate, thereby providing self-aligned P.sup.+ and N.sup.+ regions having a well defined P-N junction.

REFERENCES:
patent: 4119440 (1978-10-01), Hile
patent: 4155777 (1979-05-01), Dunkley et al.
patent: 4164436 (1979-08-01), Ura et al.
patent: 4473941 (1984-10-01), Turi et al.
patent: 4616404 (1986-10-01), Wang et al.

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