1987-10-16
1989-05-30
Miller, Stanley D.
350334, G02F 113
Patent
active
048345059
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to matrix addressable displays. In particular the invention relates to matrix addressable displays of the kind comprising a two dimensional array of switchable cells, each cell having two electrodes each carried on a surface of a respective one of two plates, each cell being switchable by means of electrical signals applied to a respective pair of electrical address lines connected to the cell, each address line within a pair being connected to a different plurality of cells within the array.
2. Description of Related Art
to overcome the problems of multiplexing the address lines in such a display, i.e. in order to identify uniquely the cell to be switched at any one time and prevent partial switching of other cells connected to one of the pair of address lines, it is known to connect each cell to its respective pair of address lines via a respective transistor, for example, a thin film transistor, i.e. the so-called `active matrix addressing` approach. FIG. 1 is a schematic circuit diagram of part of such a known display.
Referring to FIG. 1, the illustrated part of the display comprises an array of liquid crystal cells C11 to C22, each cell being represented in the figure as a capacitor. One electrode 3 of each cell is carried on the inner surface of a first insulating plate, this plate being transparent, the electrode 3 being the size of a pixel of the display, and being made of a transparent conductor such as indium tin oxide. The other electrode 5 of each cell is defined on the opposing surface of a second insulating plate, this surface carrying a series of parallel conductive column tracks 7, 9, 11 all components carried on this second plate being shown dotted in the figure.
In respect of each cell, there is provided a respective n channel thin film field effect transistor T11 to T22 carried on the first plate. One main electrode of each transistor, hereinafter referred to as a drain for convenience, is connected to the electrode 3 of each cell, whilst the gate of each transistor is connected to a selected gate address line 13, 15, 17 within a series of parallel conductive row tracks on the first plate. The second main electrode of the transistor hereafter referred to as the source for convenience, is connected to an earth line in the form of a family of conductive row tracks 19, 21 extending across the first plate paralle to the gate address lines 13, 15, 17.
In the use of the display, appropriate synchronised gate and source voltage pulses are applied to a selected pair of gate and source address lines. This then selectively addresses the one transistor which is connected to both the selected address lines. The capacitor constituted by the cell connected to the selected transistor is then able to charge up to the voltage required to give a response in the liquid crystal cell, the capacitor then being isolated when the transistor is subsequently switched off, the charge held on the capacitor being effective to switch the cell in the sense of changing the reflectivity of the liquid crystal and thus producing the required pixel image.
Such a display, however, suffers the disadvantage that a single short in a transistor gate results in the failure of the entire row of the display to which the shorted transistor belongs even a single row failure being totally unacceptable in a display. Such row failures could be turned into single pixel failure by identifying and disconnecting faulty transistors, single pixel failures being much less noticeable and thus tolerable in some applications. This process is however time consuming and expenxive particularly for large numbers of pixels.
The above known display present another problem also. Due to photolithographic defects, dust particles and similar faults, shorts may occur between adjacent pairs of gate and drain lines which are carried on the same plate as the transistors, this leading to electrical interference between adjacent rows of the display. In order to ease this problem, the
REFERENCES:
patent: 3863332 (1975-02-01), Leupp et al.
patent: 4410887 (1983-10-01), Stolov et al.
patent: 4589733 (1986-05-01), Yaniv et al.
patent: 4608558 (1986-08-01), Amstutz et al.
patent: 4632514 (1986-12-01), Ogawa et al.
patent: 4716403 (1987-12-01), Morozumi
patent: 4753518 (1988-06-01), Clerc
Bernard J. Lechner et al, "Liquid Crystal Matrix Displays", Proceedings of the IEEE, vol. 59, No. 11, Nov. 1971, pp. 1566-1579.
Clark Michael G.
Migliorato Piero
Miller Stanley D.
Pellman Anita E.
The General Electric Company p.l.c.
LandOfFree
Matrix addressable displays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Matrix addressable displays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Matrix addressable displays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2148120