Method and apparatus for detecting timing errors in digital circ

Details Method and apparatus for detecting timing errors in digital circ Method and apparatus for detecting timing errors in digital circ

1994-05-03

1995-05-23

Lall, Parshoian S.

Boots, shoes, and leggings

364578, G06F 11263, G06F 1750

Patent

active

054189314

ABSTRACT:
Disclosed is a system and method for simulating and detecting timing errors in digital circuit designs. The system consists of a logic simulator connected to various storage registers, a sequencer, and a randomizer, for simulating component functionality within the digital circuit design at sequential time increments using stored parametric data. The method includes selecting, for each component in a digital circuit design, a specific timing constraint from a range of possible timing constraint values, using a psuedo-random selection algorithm. The digital circuit is then simulated through a number of periods using this timing constraint. When an adequate number of periods have been simulated, a new set of timing constraints are selected. Timing requirement violations are detected and reported to a user.

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