Boots – shoes – and leggings
Patent
1994-05-31
1995-05-23
Harrell, Robert B.
Boots, shoes, and leggings
395800, 364DIG1, 364DIG2, 3642287, 3642292, 3642314, 3642319, 3642712, 36493142, 36493148, 36493103, G06F 1338, G06F 1336, G06F 1576
Patent
active
054189152
ABSTRACT:
In the SIMD parallel computer according to the present invention, the arithmetic unit has an instruction storage means for storing a local instruction, a selecting means for selecting any one of the common instruction and the local instruction stored in the instruction storage means, a selection control means for controlling a selecting operation of the selecting means and a means for executing the selected instruction. In an arrangement of the SIMD parallel computer of this invention is that each arithmetic part is connected to the memory via an address changeover circuit and a data changeover circuit as well. One arithmetic part is selectively connected to the memory under the selection control handled by the central control circuit. Further in the parallel computer according to the present invention for performing parallel processing of the data through communications between the plurality of processors arrayed in grids, each processor has output links extending two directions of a first diagonal line of the grid and also input links extending in two directions of a second diagonal line thereof. The output links are connected to input or output links of 3-neighbor processors. Provided is a communication circuit for selecting one of the bidirectional output links by 1 bit of a 2-bit direction signal given to establish the communication direction and one of the bidirectional input links by another 1-bit.
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Matuda Motohiko
Yuasa Taiichi
Harrell Robert B.
Philipp Timothy L.
Sumitomo Metal Industries Ltd.
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