Viterbi decoder with path metric comparisons for increased decod

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3401462, 341 94, 341107, 371 43, H03M 1300, H03M 1312

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active

054187958

ABSTRACT:
A Viterbi decoding apparatus includes a brand metric calculation circuit for calculating a branch metric for a plurality of time slots at one time by an add-compare-select-state-metric (ACS-SM) calculation circuit for performing add-compare-select (ACS) calculation an add-compare-select-state-metric calculation circuit according to a branch metric for a plurality of time slots obtained by the branch metric calculation circuit and a state metric in the preceding stage at intervals of a plurality of time slots, and a maximum likelihood sequence decision circuit for decoding input data according to the content of the path obtained through the ACS calculation, wherein on the outside of a loop composed of the ACS-SM normalization circuit and a state metric storage circuit, there is provided a normalization command circuit, whereby a decision as to the necessity for normalization, a setting of the timing of normalization, and the like are performed, and, when it is decided that normalization is necessary, the state metric normalized through a bit shifting process in the ACS-SM normalization circuit is selected before at least any one of the state metrics overflows and the selected state metric is output as a new state metric.

REFERENCES:
patent: 4905317 (1990-02-01), Suzuki
patent: 5042036 (1991-08-01), Fettweis
patent: 5208816 (1993-04-01), Seshardi et al.
Thapar, Hemant K. "A block processing method for designing high-speed Viterbi detectors", CH2655-9/89/0000-1096, pp. 1096-1100.
H. D. Lin, "Algorithms and Architectures For Concurrent Viterbi Decoding," World Prosperity Through Communications--Proceedings of the International Conference on Communications, Boston, IEEE, Jun. 1989, pp. 836-840.
K. Wen, "A New Transform Algorithm for Viterbi Decoding," IEEE Transactions on Communications, vol. 38, No. 6, Jun. 1990.

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