Method for the speedup of test vector generation for digital cir

Details Method for the speedup of test vector generation for digital cir Method for the speedup of test vector generation for digital cir

1992-12-02

1995-05-23

Ramirez, Ellis B.

Excavating

371 165, 371 19, G06F 1100

Patent

active

054187923

ABSTRACT:
The generation of a test for detecting faults in a circuit (10) can be speeded up by first selecting a successive one of a first set of faults for targeting and thereafter determining the effort required to detect a predetermined number of the first set of faults. Each of the remaining faults is then successively targeted, with the amount of effort spent to detect each of the remaining faults being adjusted in accordance with the amount of effort spent detecting the previously targeted fault. In each test cycle, faults that are untestable, or too difficult to detect during that cycle, are eliminated from consideration to improve the efficiency and speed of the test generation process.

REFERENCES:
patent: 4991176 (1991-02-01), Dahbura et al.
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5305328 (1994-04-01), Motohara et al.
"Test Generation Techniques for Sequential Circuits," by N. Gouders and R. Kaibel, published in Proceedings of the IEEE VLSI Test Symposium, pp. 221-226 (1991). (no month).
"The Back Algorithm for Sequential Test Generation," by W.--T. Cheng, published in the Proceedings, International Conference on Computer Design, at pp. 66-69 (Oct. 1988).
"GENTEST, an Automatic Test Generation System for Sequential Circuits," by W. T. Cheng and T. J. Chakraborty, published in the IEEE Transactions, Computers, vol. 22, No. 4, pp. 43-49 (Apr. 1989).

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