Method of fabricating multilevel interconnections in a semicondu

Details Method of fabricating multilevel interconnections in a semicondu Method of fabricating multilevel interconnections in a semicondu

1993-04-28

1997-03-04

Niebling, John

Fishing, trapping, and vermin destroying

437228, 437231, H01L 2144, H01L 2148

Patent

active

056078803

ABSTRACT:
The invention provides a fabrication method of multilevel interconnections for semiconductor integrated circuits. Aluminium wiring lines are formed on a first silicon oxide film overlying a silicon substrate. A second silicon oxide film is grown by a plasma chemical vapor deposition on the wiring lines and the first silicon oxide film for a specific surface treatment of either an etching with use of fluorine compounds or an ion-implantation of fluorine compounds. A third silicon oxide film is grown on the second silicon oxide film by an atmospheric pressure chemical vapor deposition with use of organic silicon compounds and an oxygen including ozone.

REFERENCES:
patent: 4670967 (1987-06-01), Hazuki
patent: 4744861 (1988-05-01), Matsunaga et al.
patent: 4800179 (1989-01-01), Mukai
patent: 4920072 (1990-04-01), Keller et al.
patent: 5212114 (1993-05-01), Grewal et al.
patent: 5244841 (1993-09-01), Marks et al.
patent: 5250468 (1993-10-01), Matsuura
patent: 5266525 (1993-11-01), Morozumi
patent: 5288664 (1994-02-01), Mukai
patent: 5312775 (1994-05-01), Fujii et al.
patent: 5319247 (1994-06-01), Matsuura
patent: 5332694 (1994-07-01), Suzuki
patent: 5344797 (1994-09-01), Pai et al.
Wolf, "Silicon Processing for the VLSI Era, vol. I", pp. 569-574, 1986, Lattice Press, month unknown.
"Low-Temperature APCVD Oxide TEOS-Ozone Chemistry for Multilevel Interconnections", IEEE, 1989, By H. Kotani et al., pp. 28.2.1-28.2.4, month unknown.
"Reaction Mechanism of TEOS and O.sub.3 Atmospheric Pressure CVD", IEEE, Jun. 11-12, 1991, By K. Fujino et al., pp. 445-447.
"Surface Modification of Base Materials for TEOS/O.sub.3 Atmospheric Pressure Chemical Vapor Deposition", J. Electrochem. Soc., vol. 139, No. 6, Jun. 1992, By K. Fujino et al., pp. 1690-1692.

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