Semiconductor memory device having hierarchical row selecting li

Details Semiconductor memory device having hierarchical row selecting li Semiconductor memory device having hierarchical row selecting li

1991-01-28

1993-03-09

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 802

Patent

active

051930749

ABSTRACT:
A memory cell array of this semiconductor memory device includes a plurality of memory cells each having one transistor and one capacitor and is divided into a plurality of large memory cell groups, and each of the large memory cell groups is further divided into a plurality of small memory cell groups. A plurality of main row-selecting lines, a plurality of sub row-selecting lines and a plurality of word lines are provided in the memory cell array, each of the large memory cell groups and each of the small memory cell groups, respectively. Main global decoders select one of the main row-selecting lines in response to an internal address signal. Sub global decoders select a sub row-selecting line associated with the selected main row-selecting line in the large memory cell group selected by a large memory cell group selecting signal. Local decoders select a word line associated with the selected sub row-selecting line in the small memory cell group selected by a small memory cell group selecting signal.

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IEEE Publication "A 15ns 1Mb CMOS SRAM", by Sasaki et al., International Solid-State Circuits Conference, 1988.

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